Hardware Acceleration of the Robust Header Compression (RoHC) Algorithm
Author
Summary, in English
In LTE base-stations, RoHC is a processingintensive
algorithm that may limit the system from serving a
large number of users when it is used to compress the VoIP
packets of mobile traffic. In this paper, a hardware-software and a
full-hardware solution are proposed to accelerate the RoHC compression
algorithm in LTE base-stations and enhance the system
throughput and capacity. Results for both solutions are discussed
and compared with respect to design metrics like throughput,
capacity, power consumption, and hardware resources. This
comparison is instrumental in taking architectural level trade-off
decisions in-order to meet the present day requirements and also
be ready to support a future evolution. In terms of throughput,
a gain of 20% (6250 packets/sec) is achieved in the HW-SW
implementation by accelerating the Cyclic Redundancy Check
(CRC) and the Least Significant Bit (LSB) encoding in hardware.
The full-HW implementation leads to a throughput of 45 times
(244000 packets/sec) compared to the SW-Only implementation.
The full-HW solution consumes more Adaptive Look-Up Tables
(7477 ALUTs) compared to the HW-SW solution (2614 ALUTs)
when synthesized on Altera’s Arria II GX FPGA.
algorithm that may limit the system from serving a
large number of users when it is used to compress the VoIP
packets of mobile traffic. In this paper, a hardware-software and a
full-hardware solution are proposed to accelerate the RoHC compression
algorithm in LTE base-stations and enhance the system
throughput and capacity. Results for both solutions are discussed
and compared with respect to design metrics like throughput,
capacity, power consumption, and hardware resources. This
comparison is instrumental in taking architectural level trade-off
decisions in-order to meet the present day requirements and also
be ready to support a future evolution. In terms of throughput,
a gain of 20% (6250 packets/sec) is achieved in the HW-SW
implementation by accelerating the Cyclic Redundancy Check
(CRC) and the Least Significant Bit (LSB) encoding in hardware.
The full-HW implementation leads to a throughput of 45 times
(244000 packets/sec) compared to the SW-Only implementation.
The full-HW solution consumes more Adaptive Look-Up Tables
(7477 ALUTs) compared to the HW-SW solution (2614 ALUTs)
when synthesized on Altera’s Arria II GX FPGA.
Department/s
Publishing year
2013
Language
English
Pages
293-296
Publication/Series
2013 IEEE International Symposium on Circuits and Systems (ISCAS)
Document type
Conference paper
Publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
Topic
- Electrical Engineering, Electronic Engineering, Information Engineering
Conference name
IEEE International Symposium on Circuits and Systems (ISCAS), 2013
Conference date
2013-05-19 - 2013-05-23
Conference place
Beijing, China
Status
Published
Project
- EIT_SOS VINNOVA Industrial Excellence Center - System Design on Silicon
Research group
- Digital ASIC
ISBN/ISSN/Other
- ISSN: 2158-1525
- ISSN: 0271-4310
- ISBN: 978-1-4673-5762-3
- ISBN: 978-1-4673-5760-9