Partitioning and Optimization of High-Level Stream Applications for Multi-Clock-Domain Architectures

Summary, in English

In this paper we propose a design methodology to partition dataflow applications on a multi clock domain architecture. This work shows how starting from a high level dataflow representation of a dynamic program it is possible to reduce the overall power consumption without impacting the performances. Two different approaches are illustrated, both based on the post-processing and analysis of the causation trace of a dataflow program. Methodology and experimental results are demonstrated in an at-size scenario using an MPEG-4 Simple Profile decoder.

• Author: Simone Casale Brunet; Ecole Lausanne; Claudio Alberti; Marco Mattavelli; Eduardo Amaldi; Jörn Janneck
• Department/s: Department of Computer Science; ELLIIT: the Linköping-Lund initiative on IT and mobile communication; Parallel Systems
• Publishing year: 2013
• Language: English
• Pages: 177-182
• Publication/Series: 2013 IEEE Workshop on Signal Processing Systems (SiPS 2013)
• Links: http://dx.doi.org/10.1109/SiPS.2013.6674501
• Document type: Conference paper
• Publisher: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Topic: Computer Science
• Conference name: 2013 IEEE Workshop on Signal Processing Systems
• Conference date: 2013-10-16 - 2013-10-18
• Conference place: Taipei, Taiwan
• Status: Published
• ISBN/ISSN/Other: ISBN: 9781467362368