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A 35 fJ/bit-access Sub-VT Memory Using a Dual-Bit Area-Optimized Standard-cell in 65 nm CMOS

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Author

Publishing year

2014

Language

English

Pages

243-246

Publication/Series

[Host publication title missing]

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Conference name

European Solid State Circuits Conference (ESSCIRC), 2014

Conference date

2014-09-22 - 2014-09-26

Conference place

Venice, Italy

Status

Published

ISBN/ISSN/Other

  • ISSN: 1930-8833