A 100-fJ/cycle Sub-VT Decimation Filter Chain in 65 nm CMOS

Summary, in English

Measurements of a sub-threshold (sub-VT) decimation

filter, composed of four half band digital (HBD) filters in

65 nm CMOS are presented. Different unfolded architectures are

analyzed and implemented to combat speed degradation. The

architectures are analyzed for throughput and energy efficiency

over several threshold options. Reliability in the sub-VT domain

is analyzed by Monte-Carlo simulations. The simulation results

are validated by measurements and demonstrate that low-power

standard threshold logic (LP-SVT) and different architectural

flavors are suitable for a low-power implementation. Silicon

measurements prove functionality down to 350mV supply, with

a maximum clock frequency of 500 kHz, having an energy

dissipation of 102 fJ/cycle.

• Author: Syed Muhammad Yasser Sherazi; Peter Nilsson; Henrik Sjöland; Joachim Rodrigues
• Department/s: Department of Electrical and Information Technology; ELLIIT: the Linköping-Lund initiative on IT and mobile communication
• Publishing year: 2012
• Language: English
• Publication/Series: 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)
• Links: http://dx.doi.org/10.1109/ICECS.2012.6463654
• Document type: Conference paper
• Publisher: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Keywords: energy dissipation; measurements; sub-threshold; half band digital (HBD) filters; 65 nm CMOS; and architectures.
• Conference name: IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2012
• Conference date: 2012-12-09 - 2012-12-12
• Conference place: Seville, Spain
• Status: Published
• Project: EIT_UPD Wireless Communication for Ultra Portable Devices
• Research group: Digital ASIC
• ISBN/ISSN/Other: ISBN: 978-1-4673-1261-5; ISBN: 978-1-4673-1261-5