A 0.28-0.8 V 320 fW D-latch for Sub-VT Memories in 65 nm CMOS

Summary, in English

The design of an ultra-low-leakage latch, suitable for subthreshold standard-cell based memories in 65nm CMOS is presented. Various latch architectures are compared in terms of leakage, area and speed. The most leakage-efficient architecture is optimized by transistor stacking and channel length stretching. The final design is supplemented with a 3-state output buffer to provide low-leakage read functionality in memory applications. Silicon measurements confirm simulation results including the reliability analysis based on Monte-Carlo simulations. The latch is fully functional at 280 mV and retains data down to a supply voltage of 220mV, consuming as little as 230fW leakage power

• Author: Babak Mohammadi; Oskar Andersson; Pascal Meinerzhagen; Syed Muhammad Yasser Sherazi; Andreas Burg; Joachim Rodrigues
• Department/s: Department of Electrical and Information Technology
• Publishing year: 2014
• Language: English
• Publication/Series: [Host publication title missing]
• Links: http://dx.doi.org/10.1109/FTFC.2014.6828618
• Document type: Conference paper
• Publisher: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Conference name: FTFC
• Conference date: 2014-05-04 - 2014-05-06
• Conference place: Monaco
• Status: Published