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A low-power 2nd-order CT delta-sigma modulator with a single operational amplifier

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Author

Summary, in English

We present a 2nd-order 4-bit continuous-time (CT) delta-sigma modulator (DSM) employing a 2nd-order loop filter with a single operational amplifier. This choice strongly reduces the power consumption, since operational amplifiers are the most power hungry blocks in the DSM. The DSM has been implemented in a 65 nm CMOS process, where it occupies an area of . It achieves an SNDR of 64 dB over a 500 kHz signal bandwidth with an oversampling ratio of 16. The power consumption is from a 800 mV power supply. The DSM figure-of-merit is 59 fJ/conversion. The CT DSM is well suited for the receiver of an ultra-low-power radio.

Publishing year

2014

Language

English

Pages

387-397

Publication/Series

Analog Integrated Circuits and Signal Processing

Volume

80

Issue

3

Document type

Journal article

Publisher

Springer

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • Delta-Sigma
  • Single-operational-amplifier
  • Low-power
  • Continuous time
  • RC loop filter

Status

Published

ISBN/ISSN/Other

  • ISSN: 0925-1030