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Benchmarking of Standard-Cell Based Memories in the sub-VT Domain in 65-nm CMOS Technology

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Author

Summary, in English

In this paper, standard-cell based memories (SCMs)are proposed as an alternative to full-custom sub-VT SRAM macros for ultra-low-power systems requiring small memory blocks. The energy per memory access as well as the maximum achievable throughput in the sub-VT domain of various SCM architectures are evaluated by means of a gate-level sub-VT characterization model, building on data extracted from fully placed,

routed, and back-annotated netlists. The reliable operation at the energy-minimum voltage of the various SCM architectures in a 65-nm CMOS technology considering within-die process parameter variations is demonstrated by means of Monte Carlo circuit simulation. Finally, the energy per memory access, the achievable throughput, and the area of the best SCM architecture are compared to recent sub-VT SRAM designs.

Publishing year

2011

Language

English

Pages

173-182

Publication/Series

IEEE Journal on Emerging and Selected Topics in Circuits and Systems

Volume

1

Issue

2

Document type

Journal article

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • reliability
  • process parameter variations
  • sub-VT operation
  • Embedded memory
  • flip-flop array
  • latch array
  • low-power

Status

Published

Research group

  • Digital ASIC
  • Elektronikkonstruktion

ISBN/ISSN/Other

  • ISSN: 2156-3365