An embedded low power FIR filter

Summary, in English

A new sampler with embedded FIR filter was designed with the charge sampling technique. The filter functions by summing the weighted current on a passive capacitor and the weighting factors are decided by the FIR coefficients. The performance of the filter can well compete with conventional analog filter but with smaller area and less power consumption. A testing chip was designed with 2 V supply, 7 mW power consumption and 0.4 mm2 area in 0.35 μm CMOS technology

• Author: Gang Xu; Jiren Yuan
• Department/s: Department of Electrical and Information Technology
• Publishing year: 2001
• Language: English
• Pages: 230-233
• Publication/Series: Proceedings of the 2001 IEEE International Symposium on Circuits and Systems,
• Volume: 4
• Links: http://dx.doi.org/10.1109/ISCAS.2001.922214
• Document type: Conference paper
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Conference name: IEEE International Symposium on Circuits and Systems, ISCAS, 2001
• Conference date: 2001-05-06 - 2001-05-09
• Conference place: Sydney, NSW, Australia
• Status: Published