Optimization and implementation of a Viterbi decoder under flexibility constraints
Author
Summary, in English
This paper discusses the impact of flexibility when designing a Viterbi decoder for both convolutional and TCM codes. Different trade-offs have to be considered in choosing the right architecture for the processing blocks and the resulting hardware penalty is evaluated. We study the impact of symbol quantization that degrades performance and affects the wordlength of the rate-flexible trellis datapath. A radix-2-based architecture for this datapath relaxes the hardware requirements on the branch metric and survivor path blocks substantially. The cost of flexibility in terms of cell area and power consumption is explored by an investigation of synthesized designs that provide different transmission rates. Two designs are fabricated in a digital 0.13- $mu{hbox {m}}$ CMOS process. Based on post-layout simulations, a symbol baud rate of 168 Mbaud/s is achieved in TCM mode, equivalent to a maximum throughput of 840 Mbit/s using a 64-QAM constellation.
Publishing year
2008
Language
English
Pages
2411-2422
Publication/Series
IEEE Transactions on Circuits and Systems Part 1: Regular Papers
Volume
55
Issue
8
Full text
Document type
Journal article
Publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
Topic
- Electrical Engineering, Electronic Engineering, Information Engineering
Status
Published
Project
- Digital ASIC: Flexible Coding and Decoding for Wireless Personal Area Networks
Research group
- Elektronikkonstruktion
- Digital ASIC
- Telecommunication Theory
ISBN/ISSN/Other
- ISSN: 1549-8328