Ultra low energy and area efficient charge pump with automatic clock controller in 65 nm CMOS

Summary, in English

A low power CMOS charge pump (CP) is proposed utilizing a new combination of charge transferring switches for a faster start-up, higher efficiency and lower reverse charge sharing. A low cost feedback mechanism observes the output voltage level and automatically switches off the clock after passing a threshold, which reduces energy dissipation by 62%. It is shown that by using one capacitor per stage, the proposed architecture reaches higher voltages compared to the competitive architectures when driving capacitive loads. The design is manufactured in a 65 nm technology, and measurement results confirm a 120% higher voltage compared to the conventional Dickson CP at 400 mV with identical area cost. The measured minimum operating voltage and highest charge pumping efficiency are 290 mV and 86%, respectively.

• Author: Babak Mohammadi; Joachim Rodrigues
• Department/s: Department of Electrical and Information Technology
• Publishing year: 2016-01-19
• Language: English
• Publication/Series: 2015 IEEE Asian Solid-State Circuits Conference, A-SSCC 2015 - Proceedings
• Links: http://dx.doi.org/10.1109/ASSCC.2015.7387491
• Document type: Conference paper
• Publisher: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Conference name: 11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015
• Conference date: 2015-11-09 - 2015-11-11
• Conference place: Xiamen, Fujian, China
• Status: Published
• ISBN/ISSN/Other: ISBN: 9781467371919