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A 128-channel discrete cosine transform-based neural signal processor for implantable neural recording microsystems

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Author

Summary, in English

A 128-channel neural signal processor for implantable neural recording microsystems is presented. The processor compresses the neural information of 128 simultaneous recording channels using discrete cosine transform, achieving a compression factor of 69 at the expense of a 5.6% root mean square error. The proposed processor is implemented on register transfer level and synthesized in a 65-nm complementary metal-oxide semiconductor process. The post-layout simulated power consumption at 1.2 V is 33.06 μW (258 nW per channel) at an area cost of 0.46 mm2

Publishing year

2015

Language

English

Pages

489-501

Publication/Series

International Journal of Circuit Theory and Applications

Volume

43

Issue

4

Document type

Journal article

Publisher

John Wiley & Sons Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • Neural processsing
  • data compression
  • ASIC
  • low power

Status

Published

Research group

  • Digital ASIC

ISBN/ISSN/Other

  • ISSN: 1097-007X