Combined scheduling and instruction selection for processors with reconfigurable cell fabric

Summary, in English

This paper presents a new method, based on constraint programming, for modeling and solving scheduling and instruction selection for processors extended with a functionally reconfigurable cell fabric. Our method models parallel reconfigurable architectures, the selection of application specific computational patterns and application scheduling. It takes also into account architectural constraints. The method provides efficient design space exploration that selects existing processor instructions and new instructions implementing computational patterns on a reconfigurable cell fabric. All instructions are scheduled enabling parallel instruction execution. Our method can be used directly for VLIW architectures by relaxing constraints concerning cell-processor data transfers. MediaBench and MiBench benchmarks have been used for evaluation and we obtained optimal results in many cases.

• Author: Antoine Floch; Christophe Wolinski; Krzysztof Kuchcinski
• Department/s: Department of Computer Science; ELLIIT: the Linköping-Lund initiative on IT and mobile communication; Parallel Systems
• Publishing year: 2010
• Language: English
• Pages: 167-174
• Publication/Series: 21st IEEE International Conference on Application-specific Systems Architectures and Processors (ASAP), 2010
• Links: http://dx.doi.org/10.1109/ASAP.2010.5540997
• Document type: Conference paper
• Publisher: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Topic: Computer Science
• Conference name: 21st IEEE International Conference on Application-specific Systems, Architectures and Processors
• Conference date: 2010-07-07 - 2010-07-09
• Conference place: Rennes, France
• Status: Published
• Project: Embedded Applications Software Engineering
• Research group: ESDLAB
• ISBN/ISSN/Other: ISSN: 2160-0511; ISBN: 978-1-4244-6966-6