Wrap-gated InAs nanowire field-effect transistor
Author
Summary, in English
Field-effect transistors (FETs) based on semiconductor nanowires (Bryllert et al., 2005) have the potential to improve certain aspects of existing planar FET technologies. The possibility to form wrap-gates gives an efficient gate coupling resulting in reduced drain-induced barrier lowering. Furthermore, lateral strain relaxation allows a new freedom in combining materials in heterostructures, where materials with different lattice constants can be combined without defects (Bjork et al., 2002). Since the transistor channel, unlike the planar FETs, is vertical, heterostructures may be used to tailor the bandstructure along the direction of current flow. In this paper, we demonstrate a new technology to fabricate vertical nanowire FETs in a process that almost exclusively relies on optical lithography and standard III-V processing techniques. We measure encouraging electrical data, including current saturation at V<sub>ds</sub> ≡ 0.15 V (for V<sub>g</sub> ≡ 0 V) and low voltage operation V<sub>th</sub> ≡ -0.15 V, and present opportunities to improve the device performance by heterostructure design
Publishing year
2005
Language
English
Pages
273-276
Publication/Series
International Electron Devices Meeting 2005
Document type
Conference paper
Publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
Topic
- Electrical Engineering, Electronic Engineering, Information Engineering
- Condensed Matter Physics
Keywords
- optical lithography
- lattice constants
- 0.15 V
- InAs
- heterostructures design
- lateral strain relaxation
- drain induced barrier lowering
- gate coupling
- semiconductor nanowires
- wrap gated nanowire
- field effect transistor
Conference name
International Electron Devices Meeting 2005
Conference date
2005-12-05 - 2005-12-07
Conference place
Washington, DC, United States
Status
Published
ISBN/ISSN/Other
- ISBN: 0-7803-9268-X