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Minimum-energy sub-threshold self-timed circuits: design methodology and a case study

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Author

Summary, in English

This paper addresses the design of self-timed energy minimum circuits, operating in the sub-VT domain. The paper presents a generic implementation template using bundled-data circuitry and current sensing completion detection. To support this, a fully-decoupled latch controller has been developed, which integrates the current sensing circuitry. The paper outlines a corresponding design flow, which is based on contemporary synchronous EDA tools, and which transforms a synchronous design, into a corresponding self-timed circuit. The design flow and the current-sensing technique is validated by the implementation of an asynchronous version of a wavelet based event detector for cardiac pacemaker applications in a standard 65nm CMOS process. The chip has been fabricated and the area overhead due to power domain separation and completion detection circuitry

is 13.6 %. The improvement in throughput due to asynchronous operation is 52.58 %. By trading the throughput improvement, energy dissipation is reduced by 16.8% at the energy-minimum supply voltage.

Publishing year

2010

Language

English

Publication/Series

2010 IEEE Symposium on Asynchronous Circuits and Systems

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Conference name

The 16th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)

Conference date

2010-05-03 - 2010-05-06

Conference place

Grenoble, France

Status

Published

Project

  • Digital ASIC: Implementation of Signal Processing Algorithms for Pacemakers

Research group

  • Elektronikkonstruktion
  • Digital ASIC

ISBN/ISSN/Other

  • ISBN: 978-1-4244-6859-1
  • ISBN: 978-1-4244-6860-7