A 65-nm CMOS Area Optimized De-synchronization Flow for sub-V-T Designs

Summary, in English

This paper proposes a process independent post layout de-synchronization flow implemented in tool command language working on designs operating in the sub-V-T regime. The overhead due to the self-timed operation is combated by introducing full-custom delay elements and latches for a standard 65-nm CMOS process. The flow offers the possibility to adjust granularity based on user requirements. Case studies with different reference designs manifested an average reduction of area and power overhead from 105% to 9% and 174% to 58% in comparison to a full standard cell de-synchronization approach.

• Author: Christoph Müller; Steffen Malkowsky; Oskar Andersson; Babak Mohammadi; Jens Sparso; Joachim Rodrigues
• Department/s: Department of Electrical and Information Technology; ELLIIT: the Linköping-Lund initiative on IT and mobile communication
• Publishing year: 2013
• Language: English
• Pages: 380-385
• Publication/Series: 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)
• Links: http://dx.doi.org/10.1109/VLSI-SoC.2013.6673313
• Document type: Conference paper
• Publisher: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Conference name: IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC)
• Conference date: 2013-10-07 - 2013-10-09
• Status: Published