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Test Planning and Test Access Mechanism Design for Stacked Chips using ILP

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Author

Summary, in English

In this paper we propose a scheme for test planning and test access mechanism (TAM) design for stacked integrated circuits (SICs) that are designed in a core-based manner. Our scheme minimizes the test cost, which is given as the weighted sum of the test time and the TAM width. The test cost is evaluated for a test flow that consists of a wafer sort test of each individual chip and a package test of the complete stack of chips. We use an Integer Linear Programming (ILP) model to find the optimal test cost. The ILP model is implemented on several designs constructed from ITC’02 benchmarks. The experimental results

show significant reduction in test cost compared to when using schemes, which are optimized for non-stacked chips.

Publishing year

2014

Language

English

Pages

1-6

Publication/Series

VLSI Test Symposium (VTS), 2014 IEEE 32nd

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • DfT (Design for test)
  • Test Architecture
  • Scan chain
  • Wrapper Chain
  • Test Scheduling
  • Test Time.
  • 3D Stacked Integrated Circuit (SIC)
  • Integer Linear Programming (ILP)

Conference name

IEEE VLSI Test Symposium (VTS)

Conference date

2014-04-13 - 2014-04-17

Conference place

Napa, CA, United States

Status

Published

Research group

  • Digital ASIC

ISBN/ISSN/Other

  • ISSN: 1093-0167