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Power Savings in Digital Filters for Wireless Communication

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Author

  • Peter Nilsson
  • Anusha Gundarapu
  • Syed Muhammad Yasser Sherazi

Summary, in English

This paper presents a methodology to reduce the power consumption, silicon area, as well as increasing the performance, in digital filters that are feasible for wireless communication circuitries. The method is based on arithmetic reductions in a wave digital filter. Basically, the multipliers are removed to reduce the number of arithmetic operations. All parameters including the dynamic and static power consumption, the silicon area, as well as the delay time are reduced substantially, without any need for trade-offs. The overall improvements in area, power consumption, and delay time, are around 50%, at an average.

Publishing year

2013

Language

English

Document type

Conference paper

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • Static Power
  • Dynamic Power
  • Digital Filters
  • Half-band Filters
  • Low Leakage
  • Integrated Circuit
  • IC
  • ASIC
  • CMOS.

Conference name

European Conference on Circuit Theory and Design (ECCTD 2013)

Conference date

2013-09-08 - 2013-09-12

Conference place

Dresden, Germany

Status

Published