Memory architecture evaluation for video encoding on enhanced embedded processors

Summary, in English

In this paper we investigate the impact of different memory configurations on performance and energy consumption of the video encoding applications, MPEG-4 and H.264. The memory architecture is integrated with SIMD extended embedded processor, proposed in our previous work. We explore both dedicated memories and multilevel cache-architectures and perform exhaustive simulations. The simulations have been conducted using highly optimized proprietary video encoding code for mobile handheld devices. Our simulation results show that the performance improvement of dedicated memories on video encoding applications is not very significant. The multilevel cache-based architecture processes approximately 17 frames/s compared to 1922 frames/s for 512 KB dedicated on-chip zero-wait state memory. Thus it is difficult to justify using dedicated memory for this kind of embedded systems, when energy consumption and cost of implementation are also considered.

• Author: Ali Iranpour; Krzysztof Kuchcinski
• Department/s: Department of Computer Science; Parallel Systems
• Publishing year: 2006
• Language: English
• Pages: 309-320
• Publication/Series: Embedded Computer Systems: Architectures, Modeling, and Simulation. Proceedings (Lecture Notes in Computer Science)
• Volume: 4017
• Links: http://dx.doi.org/10.1007/11796435_32
• Document type: Conference paper
• Publisher: Springer
• Topic: Computer Science
• Conference name: Embedded Computer Systems: Architectures, Modeling, and Simulation. 6th International Workshop
• Conference date: 2006-07-17 - 2006-07-20
• Conference place: Samos, Greece
• Status: Published
• ISBN/ISSN/Other: ISSN: 1611-3349; ISSN: 0302-9743; ISBN: 978-3-540-36410-8