A fully Integrated Standard-Cell Digital PLL
Author
Summary, in English
A fully integrated digital phase-locked loop (PLL) used as a clock multiplying circuit is designed. The PLL is made from standard cells found in almost any commercial standard cell library and therefore portable between processes in netlist format. Using a 0.35 μm standard complementary metal-oxide-semiconductor CMOS process and a 3.0 V supply voltage, the PLL is designed for a locking range of 170 to 360 MHz and occupies an on-chip area of 0.06 mm2
Publishing year
2001
Language
English
Pages
211-212
Publication/Series
Electronics Letters
Volume
37
Issue
4
Document type
Journal article
Publisher
IEE
Topic
- Electrical Engineering, Electronic Engineering, Information Engineering
Status
Published
Research group
- Elektronikkonstruktion
ISBN/ISSN/Other
- ISSN: 1350-911X