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Test Planning for 3D Stacked ICs with Through-Silicon Vias

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Author

Publishing year

2011

Language

English

Document type

Conference paper

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Conference name

Second IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits

Conference date

2011-09-22 - 2011-09-23

Conference place

Anaheim, CA, United States

Status

Published

Research group

  • Digital ASIC