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A 30dBm PA for MTC Communication in 65nm CMOS Technology

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Author

  • Johan Wernehag
  • Waqas Ahmad
  • Henrik Sjöland
  • Olof Zander
  • Vanja Plicanic Samuelsson

Summary, in English

In this paper the feasibility of using a fully integrated 65nm CMOS PA in future machine-type communication standards has been investigated. The integrated PA investigated shows a linear output power in VSWR 2:1 of minimum 24dBm. A VSWR of 2:1 with an associated 3.1dB front-end insertion loss corresponds to a VSWR of 5:1 at the antenna, which is a conservative number. The PAE at 1dB compression point is close to 40% for VSWR 1:1. Taking margin for modulation peak-to-average ratio of 5dB, the PAE at compression point -5dB is 31% at 2100MHz and 24% at 2600MHz. To show the possibility of multi-band operation the PA is centered at 2100MHz and then retuned to 2600MHz, indicating feasibility of a single high band PA. The gain of the two-stage PA is 27dB at 2100MHz and 24dB at 2600MHz. All simulated with a 3.3V output stage supply.

Publishing year

2016-04-14

Language

English

Pages

147-150

Publication/Series

2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • power amplifier
  • MTC

Conference name

LASCAS

Conference date

2016-02-28

Status

Published

Project

  • EIT_SOS VINNOVA Industrial Excellence Center - System Design on Silicon

Research group

  • Analog RF

ISBN/ISSN/Other

  • ISBN: 978-1-4673-7835-2