FPGA implementation of real-time image convolutions with three level of memory hierarchy

Summary, in English

In this paper, a customized image convolution processor with three level memory hierarchy is implemented on Xilinx VirtexE FPGAs. Due to its fully pipelined datapath for calculations and streamlined data flow architecture, the processor has the performance close to that of TI highest performance C64x processor at less than 1/8 of the clock frequency with substantial I/O bandwidth reductions. Furthermore, potential power savings are envisioned in future ASIC implementations by meaningful memory hierarchy explorations. In addition, a dedicated controller composed of Finite State Machine with incremental branch optimization architecture is developed to control all the operations in calculations and data transfer

• Author: Hongtu Jiang; Viktor Öwall
• Department/s: Department of Electrical and Information Technology
• Publishing year: 2003
• Language: English
• Pages: 424-427
• Publication/Series: [Host publication title missing]
• Links: http://dx.doi.org/10.1109/FPT.2003.1275793
• Document type: Conference paper
• Publisher: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Topic: Electrical Engineering, Electronic Engineering, Information Engineering
• Keywords: field programmable gate arrays; FPGA implementation; real time image convolutions; memory hierarchy exploration; image convolution processor; finite state machine; application specific integrated circuits; incremental branch optimization; data transfer; control system synthesis; potential power savings; ASIC implementation; I/O bandwidth reduction; clock frequency; C64x processor; streamlined data flow; Xilinx VirtexE FPGA; pipelined datapath
• Conference name: IEEE International Conference on Field-Programmable Technology (FPT)
• Conference date: 2003-12-15 - 2003-12-17
• Conference place: Tokyo, Japan
• Status: Published
• ISBN/ISSN/Other: ISBN: 0-7803-8320-6