Hardware Implementation of an Iterative Sampling Rate Converter for Wireless Communication
Author
Summary, in Swedish
Abstract in Undetermined
This paper presents a new technique for fractional sample rate conversion based on an iterative Sinc (ISRC) method. The proposed algorithm was evaluated against the Farrow re-sampler, and performance simulation targeting different signal-to-noise ratios show the ISRC qualifies for application in reconfigurable terminals. The architecture was implemented in 65nm CMOS technology, and synthesis results show that the ISRC requires at least 23% less silicon area, compared to a Farrow filter with similar performance. The generic nature of the architecture enables further area reduction by time-multiplexing.
This paper presents a new technique for fractional sample rate conversion based on an iterative Sinc (ISRC) method. The proposed algorithm was evaluated against the Farrow re-sampler, and performance simulation targeting different signal-to-noise ratios show the ISRC qualifies for application in reconfigurable terminals. The architecture was implemented in 65nm CMOS technology, and synthesis results show that the ISRC requires at least 23% less silicon area, compared to a Farrow filter with similar performance. The generic nature of the architecture enables further area reduction by time-multiplexing.
Publishing year
2010
Language
English
Publication/Series
IEEE Global Telecommunications Conference (Globecom)
Document type
Conference paper
Publisher
IEEE - Institute of Electrical and Electronics Engineers Inc.
Topic
- Electrical Engineering, Electronic Engineering, Information Engineering
Keywords
- Farrow
- re-sampling
- LTE
Conference name
IEEE Global Telecommunications Conference GLOBECOM 2010
Conference date
2010-12-06 - 2010-12-10
Conference place
Miami, FL, United States
Status
Published
Research group
- Digital ASIC
- Elektronikkonstruktion
ISBN/ISSN/Other
- ISSN: 1930-529X
- ISBN: 978-1-4244-5638-3