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Abort-on-Fail Test Scheduling for Modular SOCs without and with Preemption

På svenska

Author

  • Urban Ingelsson
  • Sandeep Kumar Goel
  • Erik Larsson
  • Erik Jan Marinissen

Summary, in English

System-on-chips (SOCs) and 3D stacked ICs are often tested for manufacturing defects in a modular fashion, enabling us to record the module test pass probability. We use this pass probability to exploit the abort-on-fail feature of automatic test equipment (ATE) and hence reduce the expected test time in the context of single-site testing. We present a model for calculation of expected test time, for which the abortable test unit can be a module test, a test pattern or a clock cycle. Given an SOC, with test architecture consisting of module test wrappers and test access mechanisms (TAMs), and given module test pass probabilities, we schedule the tests on each TAM to minimize the expected test time. We describe four scheduling heuristics, one without and three with preemption. Experimental results for the ITC’02 SOC Test Benchmarks show 3.5% and 20% reduction of expected test time in SOCs with 0.89 and 0.71 SOC test pass probability respectively, without modification of SOC or ATE. Further experiments show how accurate estimates for the module test pass probability or the distribution of pass probability over test patterns need to be to lead to effective test schedulng.

Publishing year

2015

Language

English

Pages

3335-3347

Publication/Series

IEEE Transactions on Computers

Volume

64

Issue

12

Document type

Journal article

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Engineering and Technology
  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • System-on-Chip
  • stacked integrated circuit
  • manufacturing test
  • modular test
  • reject-oriented analysis
  • abort-on- fail
  • test scheduling
  • preemptive scheduling

Status

Published

Research group

  • Digital ASIC

ISBN/ISSN/Other

  • ISSN: 0018-9340