The browser you are using is not supported by this website. All versions of Internet Explorer are no longer supported, either by us or Microsoft (read more here: https://www.microsoft.com/en-us/microsoft-365/windows/end-of-ie-support).

Please use a modern browser to fully experience our website, such as the newest versions of Edge, Chrome, Firefox or Safari etc.

Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems

På svenska

Author

  • Petru Eles
  • Krzysztof Kuchcinski
  • Zebo Peng
  • Alexa Doboli
  • Paul Pop

Editor

  • Rudy Lauwereins
  • Jan Madsen

Summary, in English

We present an approach to process scheduling based on an abstract graph representation which captures both data-flow and the flow of control. Target architectures consist of several processors, ASICs and shared busses. We have developed a heuristic which generates a schedule table so that the worst case delay is minimized. Several experiments demonstrate the efficiency of the approach.

Publishing year

2008

Language

English

Pages

15-29

Publication/Series

Design, Automation, and Test in Europe : The Most Influential Papers of 10 Years DATE

Document type

Book chapter

Publisher

Springer

Topic

  • Computer Science

Status

Published

Research group

  • ESDLAB

ISBN/ISSN/Other

  • ISBN: 978-1-4020-6487-6
  • ISBN: 978-1-4020-6488-3