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A continuous-time delta-sigma ADC with integrated digital background calibration

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Author

Summary, in English

This work presents a digital calibration technique in continuous-time (CT) delta-sigma (Δ Σ) analog to digital converter. The converter is clocked at 144 MHz with a low oversampling ratio (OSR) of only 8. Dynamic element matching is not efficient to linearize the digital to analog converter (DAC) when the OSR is very low. Therefore, non-idealities in the outermost multi-bit feedback DAC are measured and then removed in the background by a digital circuit. A third-order, four-bit feedback, single-loop CT Δ Σ converter with digital background calibration circuit has been designed, simulated and implemented in 65 nm CMOS process. The maximum simulated signal-to-noise and distortion ratio is 67.1 dB within 9 MHz bandwidth.

Publishing year

2016-11-01

Language

English

Pages

273-282

Publication/Series

Analog Integrated Circuits and Signal Processing

Volume

89

Issue

2

Document type

Journal article

Publisher

Springer

Topic

  • Signal Processing

Keywords

  • Background calibration
  • Continuous-time
  • Delta-sigma modulator
  • Digital calibration

Status

Published

ISBN/ISSN/Other

  • ISSN: 0925-1030