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Optimized Integration of Test Compression and Sharing for SOC Testing

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Author

Summary, in English

The increasing test data volume needed to test core-based System-on-Chip contributes to long test application times (TAT) and huge automatic test equipment (ATE) memory requirements. TAT and ATE memory requirement can be reduced by test architecture design, test scheduling, sharing the same tests among several cores, and test data compression. We propose, in contrast to previous work that addresses one or few of the problems, an integrated framework with heuristics for sharing and compression and a Constraint Logic Programming technique for architecture design and test scheduling that minimizes the TAT without violating a given ATE memory constraint. The significance of our approach is demonstrated by experiments with ITC-02 benchmark designs.

Publishing year

2007

Language

English

Pages

207-207

Publication/Series

[Host publication title missing]

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • testing
  • system-on-chip
  • SOC
  • test scheduling
  • memory requirements
  • test data compression
  • constraint logic programming

Conference name

Design, Automation, and Test in Europe Conference DATE07

Conference date

2007-04-16 - 2007-04-20

Conference place

Nice, France

Status

Published

ISBN/ISSN/Other

  • ISBN: 978-3-9810801-2-4