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Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si

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Author

Summary, in English

In this work, we present a novel self-aligned gate-last fabrication process for vertical nanowire metal-oxide-semiconductor field-effect transistors. The fabrication method allows for exposure dose-defined gate lengths and a local diameter reduction of the intrinsic channel segment, while maintaining thicker highly doped access regions. Using this process, InAs nanowire transistors combining good on-and off-performance are fabricated demonstrating Q = gm,max/SS = 8.2, which is higher than any previously reported vertical nanowire MOSFET.

Publishing year

2016-02-16

Language

English

Publication/Series

Technical Digest - International Electron Devices Meeting, IEDM

Volume

2016-February

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Conference name

61st IEEE International Electron Devices Meeting, IEDM 2015

Conference date

2015-12-07 - 2015-12-09

Conference place

Washington, United States

Status

Published

ISBN/ISSN/Other

  • ISBN: 9781467398930