Performance improvement for H.264 video encoding using ILP embedded processor

Summary, in English

In this paper, we examine the impact of instruction level parallelism (ILP) on the full H.264 video encoding application and give quantitative performance measures of a superscalar architecture. Most research efforts have concentrated on the data intensive parts, such as kernels but these are taking less time from the entire execution as encoders are using new, more efficient algorithms. This important fact cannot be neglected since new video encoding standards have been proposed and the amount of other than data intensive computations has increased significantly. We observed significant improvement for the entire application when using superscalar architecture with out-of-order execution scheme. Tradeoffs in superscalar performance are also evaluated with combinations of measurements from simplescalar simulator

• Author: Ali Iranpour; Krzysztof Kuchcinski
• Department/s: Department of Computer Science; Parallel Systems
• Publishing year: 2006
• Language: English
• Pages: 515-521
• Publication/Series: 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools
• Links: http://dx.doi.org/10.1109/DSD.2006.77
• Document type: Conference paper
• Publisher: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Topic: Computer Science
• Keywords: data intensive computations; superscalar architecture; instruction level parallelism embedded processor; performance improvement; H.264 video encoding standards; out-of-order execution scheme; simplescalar simulator
• Conference name: 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools
• Conference date: 2006-08-30 - 2006-09-01
• Conference place: Dubrovnik, Croatia
• Status: Published
• ISBN/ISSN/Other: ISBN: 0-7695-2609-8