An Area Efficient Single-Cycle xVDD Sub-Vth on-Chip Boost Scheme in 28 nm FD-SOI

Summary, in English

An on-chip, low power, and area efficient charge-pump (CP) that generates a multiple of the supply voltage (VDD) in a single clock cycle is presented. The proposed CP utilizes parallel cross-connected CP units, which are implemented using MIM (metal-insulator-metal) capacitors. In the target application, i.e., a sub-threshold SRAM, the capacitors are accommodated on top of the memory banks to remove their area cost, which dominates in a CP realization. In this work, 66 instances of the proposed CP are fully integrated on-chip to assist read and write operations. The design is manufactured in a commercial 28nm FD-SOI technology and different design parameters were verified by measurements. The results verify an increased system-wise performance and power efficiency at a low area overhead of 3.7%. A performance of 37.5MHz for a boost ratio of 2×, and an average energy dissipation of 41 fJ per operation, was observed at 0.36V.

• Author: Babak Mohammadi; Oskar Andersson; Xiao Luo; Masoud Nouripayam; Joachim Rodrigues
• Department/s: Department of Electrical and Information Technology; ELLIIT: the Linköping-Lund initiative on IT and mobile communication; Integrated Electronic Systems
• Publishing year: 2017
• Language: English
• Pages: 229-232
• Publication/Series: 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)
• Links: http://dx.doi.org/10.1109/ASSCC.2016.7844177
• Document type: Conference paper
• Publisher: IEEE - Institute of Electrical and Electronics Engineers Inc.
• Topic: Other Electrical Engineering, Electronic Engineering, Information Engineering
• Conference name: IEEE Asian Solid-State Circuits Conference (A-SSCC ). 2016
• Conference date: 2016-11-07 - 2016-11-09
• Conference place: Toyama, Japan
• Status: Published
• Research group: Integrated Electronic Systems
• ISBN/ISSN/Other: ISBN: 978-150903700-1