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Area and Power Reduction in DFT Based Channel Estimators for OFDM Systems

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Author

Summary, in English

This paper presents a new Hardware (HW) im- plementation proposal for Discrete Fourier Transform (DFT) based channel estimators. The presented algorithm uses the high time correlation property of the channel estimates to reduce the complexity and the power consumption by utilizing a lower number of bits for the FFT in the channel estimator, compared to a traditional approach. The idea is that the channel estimator processes the the difference between channel estimates from two Orthogonal Frequency Division Multiplexing (OFDM) symbols. The paper shows that the resulting HW could be reduced by 30 percent for logic and 15 percent for memory without performance loss in an Long Term Evolution (LTE) channel with up to 300Hz Doppler. The algorithm has been tested in realistic environments with 3GPP channel models.

Publishing year

2013

Language

English

Document type

Conference paper

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Keywords

  • Channel Estimator
  • DFT
  • FFT
  • OFDM
  • Orthogonal Frequency Division Multiplex

Conference name

NORCHIP Conference, 2013

Conference date

2013-11-11 - 2013-11-12

Conference place

Vilnius, Lithuania

Status

Published

Project

  • EIT_DARE Digitally-Assisted Radio Evolution

Research group

  • Digital ASIC