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Characterization of Border Traps in III-V MOSFETs Using an RF Transconductance Method

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Author

Summary, in English

The significant defect-induced increase in transconductance at high frequencies in some III-V MOSFETs is utilized to reveal the spatial distribution and energy profile of traps in the gate dielectric. The frequency response of the border traps is modeled as a distributed RC network inserted in the small signal model. Surface-channel InGaAs MOSFETs with Al2O3/HfO2 high-k gate dielectric are evaluated; especially the effects of inserting an InP cap layer in the gate stack.

Publishing year

2013

Language

English

Pages

53-56

Publication/Series

2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)

Document type

Conference paper

Publisher

IEEE - Institute of Electrical and Electronics Engineers Inc.

Topic

  • Electrical Engineering, Electronic Engineering, Information Engineering

Conference name

43rd Conference on European Solid-State Device Research

Conference date

2013-09-16 - 2013-09-20

Status

Published

ISBN/ISSN/Other

  • ISSN: 1930-8876