Digital Phase Locked Loops for Radio Frequency Synthesis
Author
Summary, in English
A state-of-the-art PLL must meet stringent requirements on signal purity, while dissipating increasingly lower power to lengthen battery lifetime and being capable of operating at the very low supply voltages required by modern CMOS processes. Furthermore, such a PLL should occupy a small area and coexist with very complex digital systems, which are responsible for the generation of extensive switching noise.
With the extraordinary pace of CMOS technology scaling and the attending increase in integration density, conventional analog designs are giving way to digital counterparts, which much better exploit the new silicon ecosystems. The foremost example of this momentous trend is probably the PLL, where the Digital Phase Locked Loop (DPLL) can exploit all the advantages, in terms of
programmability, reconfigurability, and adoption of advanced adaptive digital algorithms for the correction of PLL non-idealities, that are beyond the reach of the analog PLL.
In this dissertation, several IC design techniques are demonstrated, which improve the DPLL in terms of both overall architecture and individual subblocks. One DPLL has been designed and thoroughly simulated, while one Digitally Controlled Oscillator (DCO) and another DPLL have been designed, simulated, fabricated, and tested, obtaining excellent measured performance
Department/s
Publishing year
2017
Language
English
Full text
Document type
Dissertation
Publisher
Department of Electrical and Information Technology, Lund University
Topic
- Electrical Engineering, Electronic Engineering, Information Engineering
Keywords
- CMOS
- PLL
- DPLL
- VCO
- DCO
- loop filter
- DS modulator
- phase noise
- spurs
- quantization noise
- BBPD
- TDC
- DTC
Status
Published
Research group
- Integrated Electronic Systems
Supervisor
ISBN/ISSN/Other
- ISBN: 978-91-7753-420-4
- ISBN: 978-91-7753-419-8
Defence date
1 December 2017
Defence time
10:15
Defence place
lecture hall E:1406, building E, Ole Römers väg 3, Lund University, Faculty of Engineering LTH, Lund
Opponent
- Salvatore Levantino (Associate Professor)