Chip for wideband digital predistortion RF power amplifier linearisation
Author
Summary, in English
The authors present a custom chip for use in digital predistortion linearisation of RF power amplifiers. The chip is mainly implemented with systolic arrays. At maximum clock-rate, 130 MHz, the throughput is 16 Msamples/s with a 5 V supply voltage and power consumption of 1 W. A throughput of 2 Msamples/s is achieved at a 1.2 V supply voltage with 6 mW power consumption
Publishing year
1997
Language
English
Pages
925-926
Publication/Series
Electronics Letters
Volume
33
Issue
11
Links
Document type
Journal article
Publisher
IEE
Topic
- Electrical Engineering, Electronic Engineering, Information Engineering
Status
Published
ISBN/ISSN/Other
- ISSN: 1350-911X