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Instruction Selection and Scheduling for DSP Kernels

På svenska

Author

  • Mehmet Ali Arslan
  • Krzysztof Kuchcinski

Summary, in English

As custom multicore architectures become more and more common for DSP applications, instruction selection and scheduling for such applications and architectures become important topics. In this paper, we explore the effects of defining the problem of finding an optimal instruction selection and scheduling as a constraint satisfaction problem (CSP). We incorporate methods based on sub-graph isomorphism and global constraints designed for scheduling. We experiment using several media applications on a custom architecture, a generic VLIW architecture and a RISC architecture, all three with several cores. Our results show that defining the problem with constraints gives flexibility in modelling, while state-of-the-art constraint solvers enable optimal solutions for large problems, hinting a new method for code generation.

Publishing year

2014

Language

English

Pages

803-813

Publication/Series

Microprocessors and Microsystems

Volume

38

Issue

8

Document type

Journal article

Publisher

Elsevier

Topic

  • Computer Science

Keywords

  • Instruction selection
  • Scheduling
  • Custom architecture
  • VLIW
  • Constraint programming

Status

Published

Project

  • High Performance Embedded Computing

Research group

  • ESDLAB

ISBN/ISSN/Other

  • ISSN: 0141-9331